The replay scoreboard could observe instructions which have passed the replay stage. Hence, if replay occurs the replay scoreboard may well comprise the correct state to be restored to The difficulty scoreboards. The graduation scoreboard may possibly observe Guidance which have passed the graduation stage (e.g. cache misses or very long latency floating issue operations). If an exception happens, the graduation scoreboard may possibly consist of the correct point out to become restored to the replay scoreboard and The problem scoreboard.
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While in the TLB phase, the virtual tackle is translated to a Bodily address. The Actual physical handle is appeared up in the information cache 30 while in the Cache stage (and the data could be forwarded In this particular phase). Inside the Wr phase, the data comparable to a load is prepared to the sign up file 28. Lastly, in the graduation stage, the load instruction is dedicated or an exception equivalent to the load is signaled. Every single in the load/retailer units 26A-26B could implement unbiased load/retail outlet pipelines and therefore There are 2 load/shop pipelines in the present embodiment. Other embodiments may have far more or less load/retail outlet pipelines.
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The clearing on the replay scoreboards would be the pure result of the Guidance finishing, or the issue control circuit forty two and/or maybe the replay scoreboards may possibly include circuitry to carry out the clearing. Alternatively, The difficulty Manage circuit forty two may perhaps distinct both the issue along with the replay scoreboards and may not duplicate the replay scoreboards above The difficulty scoreboards.
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If it is, a replay circumstance is detected. The difficulty Management circuit 42 might sign the replay to all execution units utilizing the replay indicator. In reaction towards the replay indication, the execution units may cancel the replayed instruction and any subsequent Guidelines in software buy. The problem Manage circuit 42 could update the pipe state to point the replayed Guidance aren't from the pipe, allowing the Guidelines being reissued from the issue queue 40.
Alternatively, the pipe condition may be a counter which happens to be secure displayboards for behavioral units incremented as the instruction progresses from pipeline stage to pipeline phase. In one embodiment, the pipelines from the integer, floating stage, and load/retailer execution units tend not to stall (instruction replay could be utilised the place an instruction may in any other case stall within the pipeline). Appropriately, the pipe condition may possibly modify to another phase Every single clock cycle until finally the instruction is both canceled or graduates.
Accordingly, in these types of embodiments, The difficulty Manage circuit 42 may well not set bits within the FP EXE WAW situation and replay scoreboards 46G-46H or perhaps the FP Madd Uncooked situation and replay scoreboards 46E-46F in blocks a hundred and twenty and 124 for brief floating place Recommendations.
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The spot register number might incorporate a tad distinguishing floating place registers from integer registers, or maybe a individual sign may be supplied indicating whether the register number is undoubtedly an integer or floating point sign up (and also a independent indication of the sort of register might be stored within the destination sign up subject 216 or the opposite area 220).
These scenarios can be managed by checking the FP RAW relay scoreboard 46A for that location register on the floating position instruction and replaying the floating point instruction if a dependency is detected.
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